92 lines
3.1 KiB
C
92 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* adaptation of kernel's <asm-generic/rwonce.h>
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* See https://www.kernel.org/doc/Documentation/memory-barriers.txt
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*/
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/*
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* Prevent the compiler from merging or refetching reads or writes. The
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* compiler is also forbidden from reordering successive instances of
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* READ_ONCE and WRITE_ONCE, but only when the compiler is aware of some
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* particular ordering. One way to make the compiler aware of ordering is to
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* put the two invocations of READ_ONCE or WRITE_ONCE in different C
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* statements.
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*
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* These two macros will also work on aggregate data types like structs or
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* unions.
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*
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* Their two major use cases are: (1) Mediating communication between
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* process-level code and irq/NMI handlers, all running on the same CPU,
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* and (2) Ensuring that the compiler does not fold, spindle, or otherwise
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* mutilate accesses that either do not require ordering or that interact
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* with an explicit memory barrier or atomic instruction that provides the
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* required ordering.
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*/
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#ifndef __BR_RWONCE_H
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#define __BR_RWONCE_H
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/************ originally in <include/linux/compiler_types.h> */
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/*
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* __unqual_scalar_typeof(x) - Declare an unqualified scalar type, leaving
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* non-scalar types unchanged.
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*/
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/*
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* Prefer C11 _Generic for better compile-times and simpler code. Note: 'char'
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* is not type-compatible with 'signed char', and we define a separate case.
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*/
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#define __scalar_type_to_expr_cases(type) \
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unsigned type: (unsigned type)0, \
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signed type: (signed type)0
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#define __unqual_scalar_typeof(x) typeof( \
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_Generic((x), \
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char: (char)0, \
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__scalar_type_to_expr_cases(char), \
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__scalar_type_to_expr_cases(short), \
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__scalar_type_to_expr_cases(int), \
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__scalar_type_to_expr_cases(long), \
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__scalar_type_to_expr_cases(long long), \
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default: (x)))
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/* Is this type a native word size -- useful for atomic operations */
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#define __native_word(t) \
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(sizeof(t) == sizeof(char) || sizeof(t) == sizeof(short) || \
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sizeof(t) == sizeof(int) || sizeof(t) == sizeof(long))
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/************ originally in <asm-generic/rwonce.h> */
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/*
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* Yes, this permits 64-bit accesses on 32-bit architectures. These will
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* actually be atomic in some cases (namely Armv7 + LPAE), but for others we
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* rely on the access being split into 2x32-bit accesses for a 32-bit quantity
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* (e.g. a virtual address) and a strong prevailing wind.
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*/
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#define compiletime_assert_rwonce_type(t) \
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compiletime_assert(__native_word(t) || sizeof(t) == sizeof(long long), \
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"Unsupported access size for {READ,WRITE}_ONCE().")
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/*
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* Use __READ_ONCE() instead of READ_ONCE() if you do not require any
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* atomicity. Note that this may result in tears!
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*/
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#ifndef __READ_ONCE
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#define __READ_ONCE(x) (*(const volatile __unqual_scalar_typeof(x) *)&(x))
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#endif
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#define READ_ONCE(x) \
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({ \
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compiletime_assert_rwonce_type(x); \
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__READ_ONCE(x); \
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})
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#define __WRITE_ONCE(x, val) \
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do { \
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*(volatile typeof(x) *)&(x) = (val); \
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} while (0)
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#define WRITE_ONCE(x, val) \
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do { \
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compiletime_assert_rwonce_type(x); \
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__WRITE_ONCE(x, val); \
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} while (0)
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#endif /* __BR_RWONCE_H */
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